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The Agilent 81105A output module used with the 81104A mainframe generates all the standard pulses and digital patterns needed to test current logic technologies (CMOS, TTL, LVDS, ECL, etc.). With the optional second channel multi-level and multi-timing signals can be obtained using the internal channel addition feature. Timing values can now be swept without the danger of misleading pulses or dropouts that could cause measurement errors. Specifications. Frequency range: 1 mHz to 80 MHz. Timing resolution: 3.5 digits, 5 ps best case. Period Range: 12.5 ns to 999.5 s. Period RMS jitter: 0.001% + 15 ps (With PLL), 0.01% + 15 ps (With VCO). Period Width range: 6.25 ns to (period - 6.25 ns). Period range Accuracy: ± 5% ± 250 ps. Jitter (RMS): 0.01% + 15 ps. Additional Variable delay range: 0 ns to (period -12.5). Transition time range (10/90): 3 ns to 200 ms. Linearity: 3% typ. for transitions > 100 ns. Burst Count: 2 to 65536 (single or double pulses). Delay: Delay, phase or % of period. Double pulse delay: Double pulse and delay are mutually exclusive. Duty cycle: Set between 0.1% and 95% (subject to width limits 99.9% with overprogramming). Output connectors: BNC single-ended. Source Impedance: Selectable 50 ohm or 1 k-ohm. Accuracy: Typ. ± 1%. Max. external voltage: ± 24 V. Short circuit current: ± 400 mA max (doubles for channel addition). Base line noise: 10 mV RMS typical, 4 mV RMS typ.. Overshoot /preshoot /ringing: ± 5% of amplitude ± 20 mV.
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